Product News

With the acceleration of the intelligentization process of new energy vehicles, smart high - side switches, relying on their intelligent features and comprehensive protection functions, have been widely applied in the automotive market. The intelligent high - side switch series products of Acmic Micro have expanded accordingly and have successfully been implemented in the on - board projects of numerous customers in the fields of commercial vehicles, passenger cars, and off - road construction machinery.

It should be noted that some customers have encountered some abnormal phenomena when using competing products. This article will conduct an in - depth analysis of the abnormal phenomena of competing products and expound on the technical advantages of Acmic Micro's products.

1.Application background and abnormal phenomena

（1）Test conditions：

Supply voltage：VS=24V.

Drive signal: Input a PWM signal with 5V/500Hz and a duty cycle of 50% at the IN terminal.

Load status: The OUT terminal is unloaded.

（2）abnormal phenomena：

Phenomenon 1: The OUT output does not follow the IN control.The starting point of VOUT decline is delayed, causing the duty cycle of VOUT = 24V to rise to 60%, which does not match the 50% duty cycle set at the IN terminal.

Phenomenon 2: Prolonged total turn - off timeThe falling edge of VOUT is gentle, and the total duration from the start of turn - off to complete turn - off increases significantly, affecting the response speed of the device.

2.Analysis of abnormal phenomena

Note: Parameters such as 50nA and 1.6V involved in the following analysis are typical value examples and do not represent the exact parameters of the actual device.

Phenomenon 1: The OUT output does not follow the IN control

As shown in Figure 1-2 below, the occurrence of this phenomenon has nothing to do with the PWM frequency at the IN terminal. The reason why the duty cycle of VOUT = 24V reaches 60% when the IN terminal is at 500Hz is that the turn - off delay platform time is fixed, approximately 180us. Under high-frequency driving, the switching cycle is short, making this period more obvious.

The formation of the turn - off delay platform can be analyzed from the following three aspects:

<1> No-load condition: When the OUT terminal is under no-load condition, the drain current ID of the power MOS will drop to an extremely low level (only 50nA). At this time, the gate-source voltage VGS needs to be discharged to the lowest point of the MOSFET on-off threshold (Vth = 1.6V) to trigger the start of the MOSFET turn-off. When Vth > 1.6V, the existing voltage can maintain ID = 50nA, so VDS remains at a low value all the time, that is, the VOUT voltage remains stable, and the MOSFET cannot start to turn off.

<2> Normal loaded condition: When under normal load, the ID current is relatively large. After the enable at the IN terminal is interrupted and the gate starts to discharge, when VGS drops to 2-3V, it is no longer sufficient to support the current large current. VDS increases accordingly, and VOUT decreases synchronously.

<3> Influence of RC discharge characteristics: Due to the existence of parasitic capacitance and resistance between the gate and the source, the VGS discharge process is approximately equivalent to the discharge of an RC circuit. Since the time it takes for VGS to drop to 1.6V is much longer than the time it takes to drop to 2-3V, under no-load conditions, the flat-time from the IN turn-off to the VOUT drop is longer than that under normal load conditions.

Phenomenon 2: The total turn - off time becomes longer

The root cause of the slow falling edge of VOUT lies in the parasitic capacitance CDS between the drain and source of the MOS transistor (see Figure 4). Its equivalent capacitance value is approximately several hundred pF to several nF and decreases as VDS increases. When the MOS transistor passes through the turn-off delay platform and starts to turn off, VOUT begins to decrease and charges CDS at the same time. However, since the OUT terminal is in an unloaded state, the charging current can only rely on the weak current (50nA) provided by the internal parasitic circuit, resulting in a slow charging speed. Eventually, this leads to a gentle falling edge of VOUT and a longer total turn - off time.

3.Reactor Microelectronics product solutions

In the waveform comparison test from the IN turn-off to the complete turn-off of VOUT, Reactor Microelectronics' dual-channel high-side switches outperform competing products. Reactor Microelectronics' products have a proprietary design added to the gate-source discharge circuit, which can release the gate charge more quickly after the IN terminal is turned off, effectively reducing the turn-off delay when the load resistance is relatively large. As shown in Figure 5, the turn-off delay platform time of Reactor Microelectronics' products is only 64us, while that of competing products is 180us.

It can also be seen from the above figure that there is still a platform voltage when the competing product is turned off with a 10KΩ resistor grounded. To eliminate this platform, the ID current needs to be increased, making the VGS voltage required to turn off the MOS higher. Thus, even when the residual charge on the gate of the power transistor of the competing product is released slowly, it can still turn off quickly. For example, a resistor load less than 1kΩ needs to be connected to the OUT terminal to completely eliminate the abnormal situation of its delayed turn-off.

If you encounter any technical issues during the use of our intelligent high-side switch products, please feel free to call us for communication and consultation. The contact numbers are: 029-88827769/18009231253. Our technical team will provide you with targeted answers and better solutions.